1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to flash memory suitable for high density implementations.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate.
The typical flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S).
Data is stored in a flash memory device by controlling the amount of charge trapped in the charge storage structure. The amount of charge stored sets a threshold voltage for the memory cell in flash memory devices, which allows the data to be read.
As specifications for the values of target threshold voltages tighten for low voltage applications, and for applications that store multiple bits per cell, problems are arising with precise control over the amount of charge stored in a target cell during a program operation, and with prevention of disturbance of the charge stored in the memory cells by program and erase operations directed at other cells.
It is desirable to provide a new memory technology that provides for finer control over the charge storage in flash memory.